1. Technical Field
This invention relates to analog-to-digital converters and, more particularly, to techniques for making such converters using focused ion beam implantation techniques.
2. Discussion
Analog-to-digital (A/D) converters are widely used to convert an analog signal into a binary or digital signal. Many A/D converters are employed to interface high speed analog signals with ultra-fast digital signal processors. As the speed and level of integration of digital circuits increases, it becomes important to fabricate A/D converters and digital processing circuitry on the same semiconductor substrate. GaAs FET or Silicon complementary metal oxide semiconductor (CMOS) technology is especially attractive for this approach because of its suitability for both analog and digital applications. However, in order to be able to accomplish this, it is necessary to implement the A/D converter in such a way that it requires little area on the substrate and minimizes power dissipation, yet performs the conversion process at high speed.
High speed A/D converters are often realized using so-called "flash" type circuitry. As an example, a two-bit flash A/D converter of the prior art is shown in FIG. This converter generally includes a resistor string (R1-R4), four comparators and latches, and a decoder. In operation, the analog input voltage (V.sub.in) is applied simultaneously to all comparators and compared to corresponding fractions of the reference voltage (V.sub.ref). If the analog input voltage is greater than the fractional portion of the reference voltage at its input, the comparator output will be high; otherwise it will be low. The latches are typically implemented by flip flops, which amplify and store the output states of the comparators. The latched comparator output signals are then decoded to produce the digital outputs A1 and A0 which may be processed into binary coded decimal (BCD) format.
A CMOS comparator circuit, which can be used in the FIG. 1 embodiment, is shown in FIG. 2. During the half clock cycle when the clock voltage (.phi.) is high, the fractional share of the reference voltage (V.sub.i) is applied to the capacitor C and, at the same time, the inverter is auto zeroed, which eliminates its offset voltage. During the second half of the clock cycle, when .phi. is low, the analog input voltage (V.sub.in) is applied to capacitor C and the resulting difference (V.sub.i -V.sub.in) is amplified by the inverter and provided to the input of the latch. The minimum clock period is largely determined by the length of time required for the comparator to achieve a change of state, or by the time required by auto zeroing. This period determines the maximum sampling rate of the converter.
Some of the disadvantages of the A/D converter shown in FIGS. 1 and 2 are that the circuit speed is significantly degraded by the necessity for auto zeroing the comparator once per clock period. In addition, the parasitic capacitance of capacitor C further degrades the achievable speed. Also, the resistor ladder requires excessive area and power dissipation.
Another example of a CMOS A/D converter is disclosed in the paper by Silburt et al., "A Novel Multiple Threshold MOSFET Structure for A/D and D/A Conversion", IEEE Journal of Solid State Circuits, vol. SC-19, No. 5, October 1984. In the disclosed implementation a string of inverters is used to perform the A/D conversion. Each inverter has a unique threshold voltage. However, the threshold voltage is adjusted by varying the bias voltage of each transistors' substrate. This is a somewhat cumbersome technique to implement and has other disadvantages. For example, the optimum substrate bias voltage is temperature dependent, and each transistor requires its own temperature compensated bias supply. The technique is not applicable to CMOS/SOS or GaAs technologies, which are inherently faster than typical CMOS processes.